EC280 Digital System Design

Course Name: 

EC280 Digital System Design

Programme: 

B.Tech (ECE)

Category: 

Programme Specific Electives (PSE)

Credits (L-T-P): 

(3-0-2) 4

Content: 

Review of Combinational and Sequential logic design, digital system design and implementation options, ASICs, PLDs, FPGAs. Programmable ASICs. Digital system modeling, Hardware description based on Hardware Description Languages, VHDL/ Verilog, data path and control path synthesis, Design case studies, computer aided design tools, Design flow, commercial CAD packages, clocking techniques, Functional simulation, timing analysis, testability and fault tolerance in design.

References: 

C.H. Roth, Digital system design using VHDL, PWS Publising, 1998
Samir Palnitkar. "Verilog HDL -A Guide to Digital Design and Synthesis." Pearson Education, 1999.
Zainalabedin Navabi, “Verilog Digital System Design”, 2nd Ed., McGraw Hill, 2006.
Michael D. Ciletti, "Modeling, Synthesis, and Rapid Prototyping with the Verilog (TM) HDL", Prentice Hall 1999.
T. R. Padmanabhan and B. Bala Tripura Sundari, “Design through Verilog HDL”, John Wiley & Sons, 2004.
Peter Ashenden, The Designer’s Guide to VHDL, Morgan Kaufman, 2002
J. Bhaskar, “Verilog HDL Synthesis – A Practical Primer”, Star Galaxy Publications, 1998.
Donald Thomas and Philip R. Moorby, “The Verilog Hardware Description Language”, Springer publications, 2008.

Department: 

Electronics and Communication Engineering(ECE)
 

Contact us

Dr. U. Shripathi Acharya,  Professor and Head, 
Department of E&C, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

  • Hot line: +91-0824-2473046

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