EC432 Mapping DSP Algorithms to Architecture

Course Name: 

EC432 Mapping DSP Algorithms to Architecture

Programme: 

B.Tech (ECE)

Category: 

Programme Specific Electives (PSE)

Credits (L-T-P): 

(3-0-0) 3

Content: 

Real time signals and digital signal processing – Processor architectures General Purpose architectures and custom VLSI design, Representations of DSP algorithms dataflow graphs, recursive equations, Iteration bound, Critical paths and limits on implementation speed – Pipelining and parallel processing, Retiming methodology, Unfolding/Folding transformation, register minimization techniques Systolic architectures, mapping algorithms to array structures. Arithmetic: Fixed point, floating point and residue arithmetic, Multiply and Divide algorithms, MAC, Cordic architectures, Issues in arithmetic system design; Algorithms for fast implementation of convolution, FIR, IIR and adaptive filters, DCT, analysis of finite word length effects, Low power designs strategies.

References: 

K.K. Parhi, “VLSI Digital signal processing systems: Design and implementation”, John Wiley, 1999.
Lars Wanhammar, “DSP Integrated Circuits”, Academic Press, 1999
Sanjit K. Mitra, "Digital Signal Processing: A computer based Approach", TMH, 2006.
 

Contact us

Dr. U. Shripathi Acharya,  Professor and Head, 
Department of E&C, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

  • Hot line: +91-0824-2473046

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