VL725 Digital VLSI Testing & Testability

Course Name: 

VL725 Digital VLSI Testing & Testability


M.Tech (VLSI)




Programme Core (PC)

Credits (L-T-P): 

(3-1-0) 4


Overview of testing and verification, Defects and their modeling as faults at gate level and transistor level. Functional V/s. Structural approach to testing. Complexity of testing problem. Controllability and observability. Generating test for a signal stuck-at-fault in combinational logic. Algebraic algorithms. Test optimization and fault coverage. Logic Level Simulation – Delay Models, Event driven simulation, general fault simulation (serial, parallel, deductive and concurrent). Testing of sequential circuits. Observability through the addition of DFT hardware, Adhoc and structured approaches to DFT – various kinds of scan design. Fault models for PLAs, bridging and delay faults and their tests. Memory testing, Testing with random patterns. The LFSRs and their use in random test generation and response compression (including MISRs ), Built-in self test.


M. Abramovici, M. A. Breuer, and A. D. Friedman, Digital Systems Testing and Testable Design, IEEE Press, 1994.
M. L. Bushnel and V. D. Agarwal, Essentials of Testing for Digital, Memory and Mixed – Signal VLSI Circuits, Kluwer Academic Publishers, 2000.
Ajai Jain, Learning Module for the course - VLSI Testing and Testability, IIT, Kanpur, 2001.

Contact us

Dr. T. Laxminidhi,  Professor and Head, 
Department of E&C, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

  • Hot line: +91-0824-2473046

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