VL832 Digital Signal Processing Architectures
Course Name:
VL832 Digital Signal Processing Architectures
Programme:
M.Tech (VLSI)
Category:
Elective (Ele)
Credits (L-T-P):
(3-0-0) 3
Content:
Introduction, Data flow representation, pipelining, and parallel processing, retiming, folding, unfolding, systolic architecture design, fast convolution, algorithmic strength reduction in filters and transforms, pipelined parallel recrusive and adaptive filters, finite world length effects in DSP systems, architecture programming and applications of general purpose DSPs
Course Objective
To provide sound foundation of digital signal processing (DSP) architectures and designing efficient VLSI architectures for DSP systems
Course Outcomes
- Understand DSP architectures
- Analyze DSP architectures
- Understand pipelining, parallel processing and retiming
- Understand and analyze folding and unfolding architectures
- Understand systolic architecture design
- Understand and analyze fast convolution algorithms and algorithmic strength reduction techniques
- Understand and analyze pipelined and parallel recrusive adaptive filters
- Understand and analyze general purpose digital signal processors
References:
K K Parhi, VLSI Digital Signal Processing Systems: Design and Implementation, John Wiely, 2007
Lars Wanhammer, DSP Integrated circuits, Academic press
S. M. Kuo, B.H.Lee, Real Time Digital Signal Processing: Implementations, Applications, and Experiments with the TMS320C55X
K K Parhi and T.Nishitani (eds), DSP for multimedia systems, Marcel Dekker
