Nikhil K S

Designation: 

Assistant Professor Grade I

Date of Joining at NITK: 

Thursday, September 26, 2019

Professional Experience: 

i) Postdoctoral Research Associate, Department of Electronic Systems Engineering, Indian Institute of Science, Bangalore(September 2018 – September 2019)
ii) Assistant Professor, Department of ECE, NITK, Surathkal. (since September 2019).

Contact Details

E-mail: 

nikhilks@nitk.edu.in
nikhilks017@gmail.com

Telephone: 

+91-9444640017
Academic Background

PhD in Microelectronics (Electrical Engineering) : IIT Madras 2018;
M.E. in VLSI DESIGN : College of Engineering Guindy, Chennai, 2012;
B.Tech in ECE : Mohandas College of Engineering and Technology (University of Kerala) 2010.

Areas of Interest

Semiconductor Device Modeling
Compact modeling of devices
TCAD simulation and design of microelectronics devices
ESD and device reliability
Neuromorphic device design

Significant Projects

Name of the project : Development of design essentials for Ga2O3 based FinFET for SOC in automotive applications. (as PI)
Funding Agency : SRG, SERB-DST, Govt. of India.
Year : 2020-2022.
Funding amount : 25.90 lakhs.

Name of the project : Feasibility study and strategic analysis for the adoption of Kerala agricultural model in Lain American nations and vice versa using computational tools and machine learning techniques. (as PI)
Funding Agency : CLAS, University of Kerala.
Year : 2023-2025.
Funding amount : 8 lakhs.

Name of the project : Enhance lubricant performance in an electrical environment to overcome electrical bearing failures in electric vehicles. (as Co-PI)
Funding Agency : CRG, SERB-DST, Govt. of India.
Year : 2023-2026.
Funding amount : 14 lakhs.

Significant Publications

Journals:

  1. S. Gupta, K. S. Nikhil, N. DasGupta, A. DasGupta, and, A. Chakravorty. “ Effect of Charge Partitioning on IM3 Prediction in SOI-LDMOS Transistors," IEEE Transactions on Electron Devices, vol. 67, no. 2, pp. 606-613, Feb 2020.
  2. K. S. Nikhil, N. DasGupta, A. DasGupta, and, A. Chakravorty. “SOI-LDMOS Transistors With Optimized Partial n + Buried Layer for Improved Performance in Power Amplifier Applications," IEEE Transactions on Electron Devices, vol. 65, no. 11, pp. 4931-4937, Nov 2018.
  3. K. S. Nikhil, N. DasGupta, A. DasGupta, and, A. Chakravorty. “Analysis and Modeling of the Snapback Voltage for Varying Buried Oxide Thickness in SOI-LDMOS Transistors," IEEE Transactions on Electron Devices, vol. 63, no. 10, pp. 4003-4010, Oct 2016.
  4. N. Prasad, P. Sarangapani, K. S. Nikhil, N. DasGupta, A. DasGupta, and, A. Chakravorty. “An Improved Quasi-Saturation and Charge Model for SOI-LDMOS Transistors," IEEE Transactions on Electron Devices, vol. 62, no. 3, pp. 919-926, March 2015.
  5. K. S. Nikhil and B. Bindu. “Feasibility of Study of Conical Channel Nanowire MOSFETs for Improved Performance," Procedia Engineering, vol. 38, pp. 2364-2370, 2012.   

Conferences:

  1. V. R. Manukrishna and, K. S. Nikhil. "Improvement in Breakdown Voltage of Junctionless Power Transistor with Ga2O3 RESURF region", 4th International Conference on Innovative Trends in Information Technology, Kottayam, 2023.
  2. S. Gupta, K. S. Nikhil, A. Chakravorty, A. DasGupta, and, N. DasGupta. “Prediction of IMD behavior in LDMOS transistor amplifiers using a physics-based large signal compact model," IEEE 3rd International Conference on Emerging Electronics, Mumbai, Dec 2016.
 

Contact us

Prof. N. Shekar V. Shet, Professor and Head, 
Department of ECE, NITK, Surathkal, 
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

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