EC440 VLSI CAD

Course Name: 

EC440 VLSI CAD

Programme: 

B.Tech (ECE)

Category: 

Programme Specific Electives (PSE)

Credits (L-T-P): 

(3-0-0) 3

Content: 

Introduction to VLSI CAD: VLSI design methodologies, use of VLSI CAD tools, Algorithmic Graph Theory, computational Complexity and ROBDD; Partitioning and placement: KL algorithm, FM algorithm etc.; Floor planning: Sliced and non-sliced planning, Polish expression, Simulated annealing, partition based placement; Routing: Global routing, detailed routing, graph models, Line Search, Maze Routing, Channel routing; High Level Synthesis: Introduction to HDL, HDL to DFG, operation scheduling: constrained and unconstrained scheduling, ASAP, ALAP, List scheduling, Force directed scheduling, operator binding; Static Timing Analysis: Delay models, setup time, hold time, cycle time, critical paths, Topological vs logical timing analysis, False paths, Arrival time (AT), Required arrival Time (RAT), Slacks.

References: 

Sabih H. Gerez, Algorithms for VLSI Design Automation, John Wiley, 1998.
Majid Sarrafzadeh and C. K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1996.
Naveed Sherwani, Algorithms for VLSI Physical Design Automation, Kluwer Academic Pub., 1999.
 

Contact us

Dr. U. Shripathi Acharya,  Professor and Head, 
Department of E&C, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

  • Hot line: +91-0824-2473046

Connect with us

We're on Social Networks. Follow us & get in touch.