M. Shankaranarayana Bhat

Designation: 

Professor

Date of Joining at NITK: 

Monday, August 5, 1991

Professional Experience: 

Total 27 years at NITK.

Contact Details

E-mail: 

msbhat [at] ieee.org
msb [at] nitk.ac.in
msbhat [at] nitk.edu.in

Telephone: 

+91-824-2473507
Academic Background

Academic Backround: 

o M. Sc. (Physics) – Mangalore University o M. Tech (IE) – KREC Surathkal o Ph. D. - IISc., Bangalore o Membership of Professional Societies: 1. Senior Member, IEEE. 2. Member, IET 3. Life Member ISTE. 4. Life Member, ISSS.
Areas of Interest

Analog and mixed signal design
Submicron Devices,
Computer Architecture,
Low power VLSI Design,
High Speed Interconnects,
RF-MEMS,
Digital Image Processing.

Significant Projects

Ongoing R&D Projects:

1. Building capacity in teaching and collaborative research in sensor systems for public utilities -  Jointly with Univ. of Bermingham UK, IBM India, RBEI India, ThoughtFocus India, Srinivasa Institute of Technology, Mangalore and A J Hospital, Mangalore,  2016 - 2018 (Rs. 75.00 Lakhs) [Royal Academy of Engineering under Newton-Bhabha Programme & FICCI]

Ongoing Developmental Projects:

1. DST-FIST Project - Advanced Research Lab in RF Communications and Networks - 2016-2020  (Rs. 118 Lakhs) [DST, Govt. of India]

Completed R&D Projects:

5. Design and Development of Smart Electrical Power Distribution and Water Management system, 2016-17, [TEQIP Phase - II]    

4. Energy Harvesting Seat, 2014-16, [Aerospace Network Research Consortium, Boeing]

3. RF MEMS switches for Wideband Reconfigurable RF Microsystems, 2010-2014 (Rs. 174.5 Lakhs) [DeitY, Govt. of India]

2. RF MEMS switch for Ka-band mm-wave circuits, 2009-2013 (Rs. 67 Lakhs), jointly with Physics Dept. [ADA, Govt. of India]

1. Feasibility studies on the measurement of density in fluid mud areas using acoustic techniques, 1990-93  (Rs. 8.75 Lakhs) [DoE, Govt. of India]

Completed Developmental Projects:

3. MEMS Design Centre, 2009-2014 (Rs. 7.52 Lakhs), jointly with Physics Dept., [ADA, Govt. of India]

2. Special Manpower Development Project in VLSI Design: Phase - II, 2007-13 (Rs. 80 Lakhs) [MCIT, Govt. of India]

1. Project IMPACT – Sustainability Support Scheme, 1998-2003 (Rs. 30 Lakhs), [World Bank and DoE, Govt. of India]

Supervision of Ph.D

Completed:
1. Jagadeesh Nayak - Thesis: Automated Detection of Eye Abnormalities and Patient Data Handling (Currently Assistant Professor, BITS Dubai Campus)
2. Sooryakrishna K. - Thesis: Modeling, Analysis and Optimization of Interconnects in Deep Submicron Regime (Currently Professor, Srinivas Institute of Technology, Mangalore)
3. Bini A. A - Thesis: Image Restoration and Enhancement Using Partial Differential Equations (Currently Assistant Professor at IIIT Kottayam)
4. Jagadish D. N. - Thesis: Design of Low Power Successive Approximation Register Analog to Digital Converter (Currently Asst. Professor at IIIT Dharwad)

Ongoing:

1. Shajahan E. S. - MEMS Switches for Reconfigurable RF Micro Systems
2. Kalpana Bhat - Low Voltage Low Power Analog to Digital Converter
3. G. Ramachandra - Effective Video Encoding Techniques for Internet of Things
4. Ramshanker N. - Design and Development of Mems Based Integrated Gas Sensor
5. Jnanesh Somayaji - Performance and Reliability Codesign of Drain Extended MOS Devices for Advanced SoC Applications (Thesis submitted)
6. Sreenivasulu Polineni - Sigma -Delta Analog to Digital Converters

Significant Publications

International Journals:

15. Jagadish D. N. and M. S. Bhat, "A 14.5 f J/conversion-step 9-bit 100-kS/s Nonbinary Weighted Dual Capacitor Array based Area and Energy Efficient SAR ADC in 90 nm CMOS", IET Circuits, Devices and Systems, No. 9, 2018, ISSN 1751-8598, DOI: 10.1049/iet-cds.2018.5067 

14. E.S. Shajahan and M.S. Bhat, "Fabrication and characterisation of RF MEMS capacitive switches tuned for X and Ku bands", Int. J. Mechatronics and Automation, (Inderscience) Vol. 6, Nos. 2/3,2018, pp 143-149.

13. Sreenivasulu Polineni, M S Bhat and  Arulalan Rajan, "A 10-Bit Differential Ultra-Low-Power SAR ADC with an Enhanced MSB Capacitor-Split Switching Technique", Arabian Journal for Science and Engineering (Springer), 2018, https://doi.org/10.1007/s13369-018-3478-6

12. Shajahan, E. S., and M. S. Bhat. "Design and Fabrication of Low Voltage Inductive Tuned RFMEMS Capacitive Switches for X and Ku bands." International Journal of Applied Engineering Research 13, no. 9 (2018): 6620-6627.

11. Jhnanesh Somayaji, B. Sampath Kumar, M. S. Bhat and Mayank Shrivastava, "Performance and Reliability Codesign for Superjunction Drain Extended MOS Devices", IEEE Transactions on Electron Devices, Vol. 64, Issue 10, pp 4175-4183, 2017  (https://doi.org/10.1109/TED.2017.2733043)

10. Jagadish D. N, Laxminidhi T. and M. S. Bhat, "An 11.39 fJ/conversion-step 780 kS/s 8 bit Switched Capacitor based Area and Energy Efficient SAR ADC in 90 nm CMOS", IET Circuits, Devices and Systems, No. 11, 2017, ISSN 1751-8598, DOI:  10.1049/iet-cds.2017.0029

9. Jnanesh Somayaji and M. S. Bhat, "Triple RESURF DEMOS device design and its RF performance evaluation for Sub-Micron RF SoC platform" Jl. of Low Power Electronics (JOLPE), Vol. 13, No 4, December 2017 

8. D. N. Jagadish and M. S. Bhat, "Low Energy and Area Efficient Nonbinary Capacitor Array Based Successive Approximation Register Analog-to-Digital Converter", Journal of Low Power Electronics, 11, 436-443 (2015).

7. Sadeque Reza Khan and M. S. Bhat, “Low Power Data Acquisition System for Bioimplantable Devices”, Advances in Electronics, Hindawi Publishing  Corporation, Published online, December, 2014, Article ID 394057,  http://dx.doi.org/10.1155/2014/394057

6. A.A. Bini and M.S. Bhat, “A nonlinear level set model for image deblurring and denoising”, The Visual Computer - International Journal of Computer Graphics, SPRINGER Publications, DOI 10.1007/s00371-013-0857-6, Published Online, June 2013.

5. E. S. Shajahan, M S Bhat, “Operating Analysis of DC and RF characteristics Capacitive Coupled RF MEMS Shunt Switches by Geometrical Modifications and Material selection” in International Journal of Computer and Electrical Engineering, Vol.5, No.5, October 2013.

4. Sooryakrishna K and M. S. Bhat, "Impedance Matching in Multi-Layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications", Intl. Journal of Computer and Electrical Engineering, Vol. 4, No. 3, June 2012, pp. 345-349.

3. A. Bini and  M. S. Bhat, "Despeckling low SNR, low contrast ultrasound images via anisotropic level set diffusion", Multidimensional Systems and Signal Processing, SPRINGER Publications, Vol. 25, pp 41-65, 2014 DOI 10.1007/s11045-012-0184-5 (published online, April, 2012).

2. Sooryakrishna K. and M. S. Bhat, "Minimization of Via-Induced Signal Reflection in On-Chip High Speed Interconnect Lines", Journal of Circuits, Systems, and Signal Processing, SPRINGER Publications, Volume 31, Issue 2, April 2012, pp 689-702.

 1. Soorya Krishna K, Pramod M and M. S. Bhat, "Modeling of Single, Coupled, L and T type  Interconnects using State Space Approach" International Journal of Signal and Imaging Systems Engineering, Inderscience Publishers, Vol. 2, No. 4, pp.216–223, 2009 DOI: 10.1504/IJSISE.2009.033785

 

International Conferences      

57.  Aparna T, Sreenivasulu Polineni and M. S. Bhat, "A Three-Stage Operational Transconductance Amplifier for Delta Sigma Modulator", IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER 2018), 13-14 Aug. 2018 - Won the Best Paper Award.

56. Riya Raj , M. S. Bhat and Rekha S, "Library Characterization: Noise and Delay Modeling", IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER 2018), 13-14 Aug. 2018

55. Harpreet Mehra and M. S. Bhat, "High Level Optimization Methodology for High Performance DSP Systems using Retiming Techniques", IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER 2018), 13-14 Aug. 2018

54. Ramachandra G. and M. S. Bhat, "Compressed Sensing for Energy and Bandwidth Starved IoT Applications", IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER 2018), 13-14 Aug. 2018

53. Shreenivasa K, M. S. Bhat and Rekha S, "A Scheme for efficient and equitable use of public utilities through supervisory and distributed control", IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER 2018), 13-14 Aug. 2018

52. Baldeo Sharan Sharma and M. S. Bhat, "Design of High Performance Dual-Gate Nano-Scale In0:55Ga0:45As Transistor with modified Substrate Geometry", The 8th IEEE Annual Ubiquitous Computing, Electronics & Mobile Communication Conference, 19-21 October, 2017

51. N. Ramshanker, Kolla Lakshmi Ganapathi, Shankaranarayana M Bhat and Sangeneni Mohan "RF Sputtered CeO2 Films For Oxygen Sensing", Eighth International Conference on Smart Materials, Structures & Systems (ISSS), July 5-7, 2017

50. Baldeo Sharan Sharma and M. S. Bhat, "A Novel Dual-Gate Nano-Scale InGaAs Transistor with modified Substrate Geometry", IEEE International Conference on Innovations in Electronics, Signal Processing and Communication (ICIESC 2017), 6-7 April, 2017, Shillong, Meghalaya -  Won the Best Paper Award.

49. Baldeo Sharan Sharma and M. S. Bhat, "Improved Tri-Gate FinFET Transistor with InGaAs", 4th IEEE International Conference on Innovations in Information, Embedded and Communication Systems, 17-18 March, 2017

48. Jnanesh Somayaji and M. S. Bhat, “Analysis of Implant Parameters in High Voltage TRIPLE RESURF LDMOS for Advanced SoC Applications”, 6th IEEE Int'l Symposium on Embedded computing & system Design (ISED), Dec 15-17, 2016.

47. Sridhar Reddy N, Jagadish D. N.  and  M.S Bhat, “A Low-Energy  Area-Efficient Dual Channel SAR ADC Using Common Capacitor Array Technique”,  IEEE International Conference  on Distributed Computing, VLSI, Electrical Circuits and Robotics 2016 (DISCOVER 2016), Aug. 13-15, 2016 -  Won the Best Paper Award.

46. Suraj Hebbar, Vinay Kumar, M S Bhat and Navakanta Bhat, “Handheld Electrochemical Workstation for Serum Albumin Measurement”, IEEE International Conference on Distributed Computing, VLSI, Electrical Circuits and Robotics 2016 (DISCOVER 2016), Aug. 13-15, 2016. 

45. Suraj Hebbar,Vinay Chauhan, M.S Bhat, Navakanta Bhat, “Smart Handheld Platform For Electrochemical Bio Sensors”, 20th IEEE International Symposium on VLSI Design and Test VDAT-2016.

44. K. G. Bhat, T. Laxminidhi and M. S. Bhat, "An 8-b 1.5MS/s 2-bit per cycle SAR ADC with parasitic insensitive single capacitive reference DAC," TENCON 2015 - 2015 IEEE Region 10 Conference, Macao, 2015, pp. 1-6. doi: 10.1109/TENCON.201

43. E.S. Shajahan, M.S. Bhat and Chenna Reddy, “Inductive Tuned High Isolation RF MEMS Capacitive Shunt Switches”, 5th IEEE International Symposium on Electronic System Design (ISED),   December 15-17, 2014.

42. D. N. Jagadish and M. S. Bhat, "Low Energy and Area Efficient Non-binary Capacitor Array based SAR ADC", 5th International Symposium on Electronic System Design (ISED) 15-17 December, 2014.

41. D. N. Jagadish and M. S. Bhat, "A Low voltage Inverter based Differential Amplifier for Low Power Switched Capacitor Applications", 5th International Symposium on Electronic System Design (ISED) 15-17 December, 2014.

40.  Sadeque Reza Khan, Rajsekhar Kumar Nath and M.S. Bhat, "GSM and GUI Based Remote Data Logging System", 5th International Symposium on Electronic System Design (ISED) 15-17 December, 2014.

39. Chenna Reddy B, E S Shajahan and M S Bhat, "Design of a Triple Band-Notched Circular Monopole Antenna for UWB Applications", 11th IEEE International Conference on Wireless and Optical Communications Networks WOCN2014, 11 - 13, September 2014.

38. Ajith Sivadhasan Ramani, Ankith Giliyar Shanthiraj, Anoop Raghav Sheshadri, Arun J Thomas, Chenna Reddy, Shankaranarayana M Bhat, "Modified Sierpinski Antenna for 2.4/5.8 GHz WLAN Applications", 7th  ISSS International Conference on Smart Materials Structures Systems, July 8-11, 2014.

37.   Sadeque Reza Khan and M. S. Bhat, "GUI Based Industrial Monitoring and Control System", International Conference on Power And Energy Systems: Towards Sustainable Energy Systems (PESTSE), IEEE PES, March 13-15, 2014, Bangalore, pp:159-162.

36. Sadeque Reza Khan, Archis Banerjee, M. S. Bhat and Aritra Banerjee, "Advanced GSM Based Harvesting and Cultivation System", Digital Signal and Image Processing, Elsevier Science and Technology Publications, International Conference on Communication and Computing (ICC-2014), June 12-14, 2014, Bangalore, pp:1-8.

35. Sadeque Reza Khan, Archis Banerjee, M. S. Bhat and Aritra Banerjee, " Wireless and GUI Based Smart Office Communication System", Digital Signal and Image Processing, Elsevier Science and Technology Publications, International Conference on Communication and Computing (ICC-2014), June 12-14, 2014, pp:44-51

34. Archis Banerjee, Sadeque Reza Khan and M. S. Bhat, "Modern Home Automation System for Energy Conservation", Digital Signal and Image Processing, Elsevier Science and Technology Publications, International Conference on Communication and Computing (ICC-2014), June 12-14, 2014, pp: 98-105.

33. Bini A.A., and M.S. Bhat “A Fourth-order Partial Differential Equation model for multiplicative noise Removal in Images”, Proceedings of C2SPCA (IEEE), 10-11 Oct, 2013, India.

32. B. Vasudev Anand, E. S. Shajahan and M. S. Bhat, “RF MEMS based Loaded Line Phase Shifter for X-band Applications”, 6th ISSS conference on MEMS, Smart Materials, Structures and Systems, 6-7, September, 2013, India.

31. Chenna Reddy B, E. S. Shajahan, and M. S. Bhat, "A 180-bit C-band Phase Shifter using Interdigital Low pass/High pass Filter", ISSS National Conference on MEMS, Smart Materials, Structures and Systems, September 06-07, 2013.

30. Soorya Krishna K.  and M S Bhat, "Interconnect Delay Reduction in High Speed Clock Networks using CRLH Structure", 3rd International Engineering Symposium, 4-6 March, 2013, Kumamoto Japan.

29. Kiran Kumar Lad  and M S Bhat, "A 1-V 1-GS/s 6-bit low-power flash ADC in 90-nm CMOS with 15.75 mW power consumption ", IEEE  International Conference on Computer Communication and Informatics (ICCCI), Coimbatore, Jan 4-6, 2013, pp 1-4.

28. Vasudev Anand B, Shajahan E. S. and M. S. Bhat, “Stub mounted loaded line phase shifter using novel RF MEMS switch”, IEEE Intl. Conference on Electron Devices and Solid State Circuits (EDSSC2012), 3-5 December, 2012.

27.  B. Vasudev Anand, , E. S. Shajahan1 and M. S. Bhat, "RF MEMS based Phase Shifters for Ka-Band Applications" Fifth ISSS Conference on MEMS, Smart Materials, Structures and Systems, 21-22, September, 2012.

26. Rajeev Komar, M S Bhat and T Laxminidhi, "Switched Inverter Comparator based 0.5V Low Power 6-bit Flash ADC", 10th  IEEE Intl. Conference on Semiconductor Electronics, Kuala Lumpur, Malaysia, 19-21 September, 2012.

25. E.S.Shajahan and M S Bhat, "Tuned Dual Beam Low Voltage RF MEMS Capacitive Switches for X – Band Applications", 10th IEEE Intl. Conference on Semiconductor Electronics, Kuala Lumpur, Malaysia, 19-21 September, 2012.

24. Rajeev Komar, M. S. Bhat and  T. Laxminidhi, "A 0.5V 300µW 50MS/s 180nm 6-bit Flash ADC using inverter based comparators",  Intl. Conference on Advances in Engineering, Science and Management (ICAESM), March 2012, pp. 331 - 335.

23. Soorya Krishna K. and M. S. Bhat, "Zero delay clocking system in GHz frequency regime using CRLH metamaterial structure", Intl. Conference on Devices, Circuits and Systems (ICDCS), March 2012, pp. 206 - 210.

22. Pankaj Shrivastava, Kalpana G. Bhat, Tonse Laxminidhi, and M. S. Bhat. "A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC", Third IEEE International Conference on Emerging Applications of Information Technology (EAIT), 2012, pp. 462-466.

21. E. S. Shajahan and M. S. Bhat, "Operating Analysis of DC and RF Characteristics of RF MEMS Capacitive coupled Shunt Switches by Geometrical Modifications and Material Selection", 4th Intl. Conference on Electronics Computer Technology - ICECT 2012.

20.  Bini A A and M S Bhat, Selective Image Smoothing and Feature Enhancement using modified shock filters, 8th International Conference on Electrical Engg./ Electronics, Computer, Telecommunications & information Technology Association (ECTI_CON), 17 -19 May, 2011, Thailand, pp.991-994.

19. Soorya Krishna K and M S Bhat, Impedance Matching in Multi-layer Interconnect Structures to Minimize Signal Reflections in High Speed Applications, Proc. Of International conference on Signal Acquisition and Processing (ICSAP), Singapore, IACSIT 2010, 26-28 February., 2011.

18. A.A. Bini,  M. S. Bhat, and P. Jidesh, “An Adaptive Total Variation Model with Local Constraints for Denoising Partially Textured Images”, Proc. of International conference on Graphics and Image Processing (ICGIP), Manila, Philippines, IACSIT 2010, 4-5 Dec 2010.

17. Soorya Krishna, M S Bhat, “Impedance matching for the reduction of via induced signal reflection in on chip high speed interconnects, IEEE International Conference on Communication, Control & Computer technologies, Tamilnadu, 7-10th October 2010.

16. Soorya Krishna, K, Pramod, M and M S Bhat, “Estimation of interconnect metrics using state space approach”,  Proceedings of  International Conference on Industrial and Information Systems (ICIIS 2010) NITK Surathkal, India, July 29 – Aug 1, 2010,

15. Soorya Krishna, K  and M S Bhat, “Performance enhancement in high speed on-chip interconnect lines”,  Proceedings of  International Conference on Industrial and Information Systems (ICIIS 2010) NITK Surathkal, India, July 29 – Aug 1, 2010.

14. Soorya Krishna K,  M S Bhat, “Quasi resonant interconnect network using active inductor”, 24th Indian Engineering Congress, NITK Surathkal, 10th to 13th December 2009.

13. Rachit I Kushalappa and M S Bhat, “AutoLibGen: An open source tool for standard cell library characterization at 65nm technology”, International conference on Electronic Design, Penang, Malaysia, 1-3 Dec 2008.

12.  Narendra Konidala and M S Bhat, “Design of CMOS RF front-end for IEEE 802.11b”, International conference on Electronic Design, Penang, Malaysia, 1-3 Dec 2008.

11.  Rajashekar Guntapally and M S Bhat, “Design of Resolution Adaptive TIQ flash ADC using AMS 0.35um Technology”, International conference on Electronic Design, Penang, Malaysia, 1-3 Dec 2008.

10.  Sooryakrishna and M S Bhat, “Model order reduction and interconnect delay estimation using state space approach”, International conference on Emerging Microelectronics and Interconnection Technology EMIT-08, IISc, Bangalore, 15-18 Dec, 2008.

9. Steevan Rodrigues and M S Bhat, Impact of Process Variation Induced Transistor Mismatch on Sense Amplifier Performance, ADCOM 2006, NITK, Surathkal Dec 20-23, 2006

8. M. S. Bhat, Rekha S and H. S. Jamadagni, Extrinsic Analog Synthesis using Piecewise Linear Current-Mode Circuits, IEEE International Conference on VLSI Design, Hyderabad, Jan 3-7, 2006

7. M. S. Bhat, S. Rekha and H. S. Jamadagni,  An Extrinsic Method for the Synthesis of Analog Functions using Non-Linear Current-Mode Circuits, 2nd Indian International Conference on Artificial Intelligence (IICAI-05),  Pune, Dec. 20-22, 2005.

6. M. S. Bhat, S. Rekha and H. S. Jamadagni,  An Extrinsic Method of Evolutionary Synthesis of Multiple-Valued Arithmetic Functions using Genetic Algorithms, 2nd Indian International Conference on Artificial Intelligence (IICAI-05),  Pune, Dec. 20-22, 2005.

5. M. S. Bhat, Rekha S and H. S. Jamadagni, Multi-level Current-mode Signaling for inter-module communication in SOC Designs, Asia and South Pacific International Conference on Embedded SOCs (ASPICES 2005), Bangalore, July 5 – 8, 2005,

4. M. S. Bhat, and H. S. Jamadagni, “Power optimization in current mode circuits” , Proc. of 18th International Conference on VLSI Design, 2005, 3-7 January, Kolkata, India, pp. 175-180.

3. M. S. Bhat, and H. S. Jamadagni, “Static Power Minimization in Current-Mode Circuits”, .Proceedings of the Intl. conference,  Asia and South Pacific Design Automation Conference, 2005, 18-21 January, China, Vol.2, 1220 -1223.

2. M. S. Bhat and H. S. Jamadagni, Complexity Estimation and Evolutionary Network Synthesis of Multiple Valued Logic based on Functional Smoothness and Entropy Measures, Proceedings of First World Congress on Lateral Computing, Bangalore, Dec 17-19, 2004

1. M. S. Bhat, Rekha S and H. S. Jamadagni , Design of Low Power Current-Mode Flash ADC , Proceedings of IEEE international conference, TENCON, Chiang Mai, Thailand, Nov 21-24, 2004

National Conferences

11.  E. S.Shajahan and M. S. Bhat, "Pull-in analysis of RF MEMS shunt capacitive switches", Proc. of National Conference on Advanced Technologies in Electrical and Electronic Systems (ATEES2012), Belgaum, 17-18  Feb, 2012.

10.  Rajeev Komar, M S Bhat and Tonse Laxminidhi, " Ultra Low Power 6-bit Flash ADC using 0.5V supply in 180nm CMOS Technology", Proc. of National Conference on Advanced Technologies in Electrical and Electronic Systems (ATEES2012), Belgaum, 17-18  Feb, 2012. 

9.  G. Umesh, Piyush Bhat, and M.S. Bhat, “MEMS RF Switch for CPW Circuits”, COMSOL Conference, Bangalore, Oct. 29-30, 2010.

8.  Piyush Bhatt, K.Natarajan, R.Gandhi, G. Umesh and  M. S. Bhat, “Design and Fabrication of Tunable RF MEMS Shunt Switches”, Proc. of  Fourth ISSS National Conference on Microsystems, Smart Materials, Structures (ISSS-2010), VNIT, Nagpur, Sept. 30 – Oct. 1, 2010.

7. K Soorya Krishna, M S Bhat, “Crosstalk estimation in coupled interconnect lines using state space approach”, VLSI Design & Test Symposium 2010 (VDAT 2010), Chandigarh, 6-9th July 2010.

6. M. S. Bhat, Rekha S and H. S. Jamadagni, Synthesis of Multiple-Valued Arithmetic Functions using Evolutionary Process, IEEE VLSI Design and Test Symposium,  Aug. 10-13, 2005, Bangalore.

5. M.S.Bhat, Rekha S and H. S. Jamadagni, Multi-level Current-mode Signaling for Long High-Speed Interconnects, IEEE VLSI Design and Test Symposium, Aug. 10-13, 2005, Bangalore.

4. M. S. Bhat and H. S. Jamadagni, Complexity Estimation and Network Synthesis based on Functional Smoothness and Entropy Measures, Proceedings of IEEE INDICON, IIT Kharagpur, Dec 20-22, 2004

3.  M. S. Bhat and H. S. Jamadagni, Design of Current-mode Flash ADC , Proceedings of VLSI Design and Test workshop, VDAT, Mysore, Aug 26-28, 2004

2. M. S. Bhat, Rekha S and H. S. Jamadagni, Design of Current-mode CMOC Multiple-Valued Latch,  Proceedings of VLSI Design and Test workshop, VDAT, Mysore, Aug 26-28, 2004

1. M.S. Bhat,  G.K. Gopal, Pavan Vittal, Panchakshari “Speed area  optimization in  SRAM  based FPGAs”, VDAT National conference, Bangalore, August 18-20, 2002

Achievements

  Fellowships

  • Institute research grant for research interaction with University of Southern California, LA and Northeastern University, Boston, USA (June – July 2015)

  • TEQIP Fellowship  for academic interaction with Michigan State University, University of Michigan, Western Michigan University and University of Colorado at Colorado Springs, USA (June-July 2014).

  • ERASMUS MUNDUS Visiting Researcher Fellowship (May-July 2009) to carry out joint research with Technical University Eindhoven, Netherlands.

  • TEQIP Fellowship (June-July 2008) for academic interaction with Technical University Eindhoven and Technical University Delft, The Netherlands.

  • UGC Fellowship (2002-2005) for Ph. D Programme at IISc, Bangalore

  • UK- India REC Fellowship (1997-98) as visiting researcher at University of Manchester Institute of Science and Technology (UMIST), Manchester, UK

  • AICTE Fellowship for the Masters’ programme (1987-1989) at KREC Surathkal

US patents Filed  :     

1.  Omprakash, M.S. Bhat, Sumam David and U. Sripati, “Alternative means for conductor based short distance signal/data transfer”, - Pub. No WO/2009/136414, Pub Date  12-11-2009, Intl. Appln No, PCT/IN2009/000257 Intl. Filing Date 29-04-2009 (https://patentscope.wipo.int/search/en/detail.jsf?docId=WO2009136414)

   Indian Patents Filed :

1.  Laxminidhi T., M. Shankaranarayana Bhat and Jagadish D. N., “Switched Capacitor Integrator based Successive Approximation Register Analog to Digital Converter Circuit and Conversion Method Thereof”", filed at Indian Patent Office, Chennai – No. 3549/CHE/2014 on18/06/2014. Publication date: 14/01/2016. Request for Examination date: 14/01/2016.

2.  M Shankaranarayana Bhat and Jagadish D. N., “Successive Approximation Register Analog to Digital Converter Circuit and Conversion Method Thereof”" filed at Indian Patent Office, Chennai – No. 4777/CHE/2013 on 18/11/2013. Publication date: 24/04/2015. Request for Examination date: 15/05/2015.

3. Shankaranarayana Bhat and Jagadish D. N., “SAR ADCfiled at Indian Patent Office, Chennai – No. 2372/CHE/2013 on 30/05/2013. Publication date: 06/02/2015. Request for Examination date: 05/04/2017.

3.  Omprakash, M.S. Bhat & U. Sripati – “Alternative means for conductor based short distance signal/data transfer” – Patent filed  at Indian Patent Office, Chennai - No. 1076/CHE/2008 on 30-04-2008.  Publication date: 21/12/2012. Request for Examination date: 17/04/2012.

 

Contact us

Dr. T. Laxminidhi,  Professor and Head, 
Department of E&C, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

  • Hot line: +91-0824-2473046

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