Course Name: 



B.Tech (ECE)


Programme Specific Electives (PSE)

Credits (L-T-P): 

(3-1-0) 4


Introduction to VLSI design automation: VLSI design methodologies, use of VLSI EDA tools, Algorithmic Graph Theory, computational Complexity; Partitioning: KL algorithm, FM algorithm, EIG Algorithm, Simulated Annealing. Floorplanning and placement: Sliced and non-sliced planning, Polish expression, Simulated annealing, partition based placement; ILP & mathematical programming, partition based, force directed, Fast-Place, quadratic placement algorithms. Routing: Global routing, detailed routing, graph models, Line Search, Maze Routing, Channel routing; via minimization, clock and power routing. High Level Synthesis: Introduction to HDL, HDL to DFG, operation scheduling: constrained and unconstrained scheduling, ASAP, ALAP, List scheduling, Force directed scheduling, operator binding; Static Timing Analysis: Delay models, setup time, hold time, cycle time, critical paths, Topological vs logical timing analysis, False paths, Arrival time, Required arrival Time, Slacks. Advanced VLSI Design Automation: Physical Synthesis, Optical Proximity correction, Interconnect issues.


Naveed Sherwani, Algorithms for VLSI Physical Design Automation, 3rd ed., Kluwer Academic Pub., 1999
Majid Sarrafzadeh and C. K. Wong, An Introduction to VLSI Physical Design, McGraw Hill, 1996.
Sabih H. Gerez, Algorithms for VLSI Design Automation, John Wiley, 1998
Sung Kyu Lim, Practical Problems in VLSI Physical Design Automation, Springer, 2008
Sadiq M. Sait & Habib Youssef, VLSI Physical Design Automation: Theory and Practice, World Scientific Publishing, 1999


Electronics and Communication Engineering(ECE)

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Prof. N. Shekar V. Shet, Professor and Head, 
Department of ECE, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

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