EC801 Logic Synthesis Techniques

Course Name: 

EC801 Logic Synthesis Techniques


M.Tech (VLSI)


Elective (Ele)

Credits (L-T-P): 

(4-0-0) 4


Introduction to Computer aided synthesis and optimization. Hardware Modeling. Advanced Boolean Algebra and Applications, Shannon co-factors, satisfiability and cover, Binary Decision Diagrams, Representing Boolean functions, ROBDD, ITE operator, Variable ordering- choice of variables, application of BDD to synthesize Boolean functions, Two level combinational logic optimization, Multiple level combinational optimization. Sequential logic optimization. Cell Library Binding. Algorithms for Technology mapping – Structural and Boolean matching, Simulation & Static Timing analysis - Event driven simulation – zero delay, unit delay and nominal delay simulation, Timing analysis at the logic level, Delay models, Delay graph, static sensitization, State of the art and future trends: System level synthesis and hardware software co-design.


Giovanni De Micheli, Synthesis and Optimization of Digital Circuits, McGraw Hill, 1994.
Srinivas Devadas, Abhijith Ghosh and Kurt Keutzer, Logic Synthesis”, Kluwer Academic, 1998.
G. D. Hachtel and F. Somenzi, Logic Synthesis and Verification Algorithms, Kluwer Academic Publishers, 1996.
S. Hassoun and T. Sasao, (Editors), Logic Synthesis and Verification, Kluwer Academic publishers, 2002
NPTEL Video Lectures


Electronics and Communication Engineering(ECE)

Contact us

Prof. N. Shekar V. Shet, Professor and Head, 
Department of ECE, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

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