Overview of testing and verification, Defects and their modeling as faults at gate level and transistor level. Functional V/s. Structural approach to testing. Complexity of testing problem. Controllability and observability. Generating test for a signal stuck-at-fault in combinational logic. Algebraic algorithms. Test optimization and fault coverage. Logic Level Simulation – Delay Models, Event driven simulation, general fault simulation (serial, parallel, deductive and concurrent). Testing of sequential circuits. Observability through the addition of DFT hardware, Adhoc and structured approaches to DFT – various kinds of scan design. Fault models for PLAs, bridging and delay faults and their tests. Memory testing, testing with random patterns. LFSRs and their use in random test generation and response compression (including MISRs ), Built-in self-test.