T. Laxminidhi

Designation: 

Professor & Head

Date of Joining at NITK: 

Wednesday, October 18, 2000

Professional Experience: 

Total:14 years at KREC/NITK as regular faculty and 2 years at
KREC as Temporary Lecturer (05-09-1998 to 17-10-2000)

Contact Details

E-mail: 

laxminidhi_t[at]yahoo[dot]com
laxminidhi_t[at]nitk[dot]edu[dot]in

Telephone: 

+91-824-2473505
Academic Background
Ph.D.: Indian Institute of Technology Madras, 2008, M.Tech.: Karnataka Regional Engineering College (Mangalore University), 1998, B.E: Nitte Mahalinga Adyanthaya Memorial Institute of Technology (Mangalore University),1996.
Areas of Interest

Analog & Mixed Signal Design, Power Management Circuits.

Significant Projects

R&D Project:

On-going:

  1. Co-chief investigatorfor MeitY sponsored project – “Special Manpower Development Project - Chips to System Design (SMDP-C2SD)” – 2015-2020.
  2. Co-Investigator for IMPRINT project “Development of cost effective Radiofrequency ablation system and magnetic hyperthermia equipment for thermal therapies
  3.  of cancerous rumors", funded by Science and Engineering Research Board (SERB) with an outlay of Rs. 45.94 Lakhs,  2019-2021.

Completed:

1.      Co-investigator TEQIP-III sponsored R&D project on “Design, Development and Commissioning of Automatic Warning System for Unmanned Level Crossings of Indian Railways - in Collaboration with Southern Railways, Palakkad Division.” with an outlay of Rs. 4 Lakhs (2016-17).

  1. Co-investigator for DIT sponsored R&D project titled “RF MEMS Switches for Wide-band Reconfigurable RF Micro-systems”. The cost of the project is Rs. 175 Lakhs, (2010-2013).

Consultancy Activities

                  Technical Consultant to Corporation Bank, Syndicate Bank and Vijaya Bank for the procurment of Note Sorting Machines with Counterfeit note detection  capability . – Since 2009  for purchasing Currency Sorting Machines   The total consultancy revenue earned is about Rs. 60 Lakhs. The consultancy involved

(a)    Framing the technical specifications

(b)   Technical evaluation of the received tenders

(c)    Framing Stress test procedure for carrying out stress tests on two machines of each vendor who is qualified in the Technical evaluation of the tender.

(d)   Carrying out critical stress tests on the machines

(e)    Bring out any shortfalls in machines to the authorities of Corporation Bank.

(f)    Recommending the machines, which have qualified the stress test, for the opening of financial bids.

ASIC Chip Designs

  1. Designed Three ASIC chips as part of Ph.D. thesis.

(a)    2 chips : 70MHz-500 MHz programmable bandwidth Chebyshev low-pass continuous time Gm-C filters designed in 350 nm CMOS process

(b)   44 MHz – 300 MHz programmable bandwidth Chebyshev low-pass continuous time Active-RC filter designed in 180 nm CMOS process. 

2. India Chip Program Program (Funded by SMDP-VLSI Project)

Designed a 2 Msps Successive Approximation Register ADC in 180 nm CMOS technology. The Chip had 3 designs, two from NITK (one analog design and one digital design) and one from NIT Tiruchirapalli. The chip designed in 180 nm CMOS process from UMC Technologies  was integrated at NITK.

3. Designs of two of my Ph.D. Students and  one M.Tech. (Research) student have been realized on silicon as a single chip in 180 nm process from UMC Technologies. 

4. Chip as part of SMDP-C2SD : A  Phase-Locked Loop was designed for generating 100 MHz clock and fabricated through Semiconductor Laboratory.

RF MEMS Switches for Wideband Reconfigurable RF Microsystems

·         Role: Co-investigator   (Chief Investigator : Dr. M.S. Bhat)

·         Sponsoring Agency: Department of Electronics and Information Technology (DeitY), 6, CGO complex, New Delhi.

·         Project Outlay: Rs. 175 Lakhs

·         Project Duration: 3 years, 6 months (July 2010 to December 2013)

·         Status: Completed

Supervision of Ph.D

2 completed, 2 submitted and 4 ongoing

Completed Ph.D. thesis titles:

  1. Rekha S. - “Integrated Active-RC Continuous Time Filters for Low Voltage and Low Power Applications”
  2. Vasantha M.H. “Low Power Integrated Continuous-Time Transconductance-Capacitor Filters Targeted to Operate on 0.5V Supply Voltage“
Significant Publications

    International Journals:

  1. KG Bhat,T Laxminidhi, MS Bhat,  “A compact 4-to-8-bit nonbinary SAR ADC based on 2 bits per cycle DAC architecture”  Sādhanā 44 (6), 137, 2019.
  2. S Rekha, VM Harishchandra, T Laxminidhi, “Ultra-low voltage, power efficient continuous-time filters in 180 nm CMOS technology”, IET Circuits, Devices & Systems (in Digital Library), 2019.
  3. JRM Krishna, T Laxminidhi, Widely tunable low-pass gm−C filter for biomedical applications”  IET Circuits, Devices & Systems 13 (2), pp 239-244, 2018.
  4. Y Kaliyath, T Laxminidhi, “A 1.8 V 8.62 µW Inverter-based Gain-boosted OTA with 109.3 dB dc Gain for SC Circuits”, IETE Journal of Research, 1-9, 2018.
  5. JD Narasimaiah, L Tonse, MS Bhat, “11.39 fJ/conversion-step 780 kS/s 8 bit switched capacitor-based area and energy-efficient successive approximation register ADC in 90 nm complementary metal–oxide–semiconductor”, IET Circuits, Devices & Systems, 12 (3), 249-255, 2017
  6. S Rekha, T Laxminidhi, “Common mode feedback circuits for low voltage fully-differential amplifiers” Journal of Circuits, Systems and Computers 25 (10), 1650124, 2016
  7. S Rekha, T Laxminidhi, “0.5 V, 5 MHz active-RC biquad filter in 90 nm CMOS technology”,  International Journal of Circuits and Architecture Design 2 (2), 142-154, 2016.
  8. Jagadish D. N, Laxminidhi T. and M. S. Bhat, "An 11.39 fJ/conversion-step 780 kS/s 8 bit Switched Capacitor based Area and Energy Efficient SAR ADC in 90 nm CMOS", IET Circuits, Devices and Systems, No. 11, 2017, ISSN 1751-8598, DOI:  10.1049/iet-cds.2017.0029
  9. Rekha S. and Laxminidhi T., “ 0.5 V, 5 MHz Active-RC Biquad filter in 90 nm CMOS Technology” –  Int. J. Circuits & Architecture Design, Inderscience Publications, Vol.2, No. 2, 2016, pp. 142-154, Feb. 2017. (CNPIEC, Google Scholar, Proquest).
  10. Rekha S. and Laxminidhi T.,“Common Mode Feedback circuits for Low Voltage Fully Differential Amplifiers” - Journal of Circuits, Systems and Computers (JCSC), World Scientific Publishing Company, Vol. 25, No.10, 1650124 – 1-12 pages, May 2016. (SCIE, Scopus Indexed).
  11. Rekha S. and Laxminidhi T., “Low voltage, Low power Chebyshev filter in 0.18 µm CMOS Technology”, Journal of Circuits, Systems and Computers (JCSC), World Scientific Publishing Company,  Vol. 22, No. 7, 1350053 – 1-18 pages, July 2013. (SCIE, Scopus Indexed).
  12. Vasantha M. H. and Tonse Laxminidhi,  "Two-Port Transmission Line Parameters Approach for Accurate Modeling and Design Centering of Integrated Continuous-Time Filters”, International Journal of Advanced Computer Research (ISSN (print):2249-7277, ISSN (online): 2277-7970) Volume-2, Number-4, Issue-6, pp:156-162 December 2012.
  13. Rekha S. and Laxminidhi T., “A low power, fully differential bulk driven OTA in 180 nm CMOS Technology”, International Journal of Computer and Electrical Engineering(IJCEE) ISSN: 1793-8163, Vol. 4, No. 3, June 2012.
  14. Pramod M. and T. Laxminidhi “Low Power  Continuous Time Common Mode Sensing for Common Mode Feedback Circuits”,  Journal of Circuits, Systems, and Computers, Vol19, No.3, May 2010, pp 519-528.
  15. T. Laxminidhi, V. Prasadu and S. Pavan “Widely Programmable High Frequency Active-RC Filters in CMOS Technology”  IEEE Transactions on Circuits and Systems – I : Regular Papers, February 2009.

    International Conferences:

  1. JR MK, S Polineni, L Tonse, “91dB Dynamic Range 9.5 nW Low Pass Filter for Bio-Medical Applications”,  2018 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 453-457
  2. SS Kuncham, M Gadiyar, S Din, KK Lad, T Laxminidhi, “A Novel Zero Blind Zone Phase Frequency Detector for Fast Acquisition in Phase Locked Loops”, 2018  31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 167-170.
  3. S Sankaranarayanan, KC Vinod, A Sreekumar, T Laxminidhi, V Singhal, R. Chauhan, “Single Inductor Dual Output Buck Converter for Low Power Applications and Its Stability Analysis”, 2018  31st International Conference on VLSI Design and 2018 17th International Conference on Embedded Systems (VLSID), 347-352.
  4. Y Kaliyath, T Laxminidhi, ”A 1.8 V 11.02 μW single-ended inverter-based OTA with 113.62 dB gain”, 2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 237-241.
  5. PK Hareesh, T Laxmindhi, “1.5°C accurate CMOS temperature sensor with a single point trim at 85°C”, 2016 IEEE Distributed Computing, VLSI, Electrical Circuits and Robotics (DISCOVER), 62-66.
  6. MV Prajwal, BS Srinivas, S Shodhan, MKJ Reddy, T Laxminidhi, “A Gyrator Based Output Resistance Enhancement Scheme for a Differential Amplifier”, 2016 29th International Conference on VLSI Design and 2016 15th International Conference on Embedded Systems (VLSID), 146-150.
  7. Rekha S. and Laxminidhi T., “Ultra low power Active-RC filter in 180 nm CMOS technology”, Proc.of 11th International Workshop IEEE on Electronics, Control, Measurement, Signals and their application to Mechatronics (ECMSM), Toulouse, France, June 21-23, 2013.
  8. Vasantha M.H. and Tonse Laxminidhi,“Fixed Transconductance Bias Circuit for Low Voltage Bulk-Driven Transconductor”,in proceedings of International Conference on Communication, VLSI and Signal Processing (ICCVSP–2013), Feb.20–22 2013, 271-274.
  9. Rekha S. and Laxminidhi T., “Effect of Finite gain and Bandwidth of feedforward compensated OTA on Active-RC integrators: A case study”, International Symposium of Electronic System Design (ISED) 2012, Kolkata, December 19-22, 2012.
  10. Vasantha M.H. and Tonse Laxminidhi, “0.5 V, Low Power, 1MHz Low Pass Filter in 0.18 μm CMOS Process”, in proceedings of IEEE Third International Symposium on Electronic System Design, Dec 18–21, 2012, pp.33–37.
  11. Shrivastava, P., Bhat, K.G. Laxminidhi T. and Bhat, M.S. , “ A 500 kS/s 8-bit charge recycle based 2-bit per step SAR-ADC”,   in proceedings of Third International Conference on Emerging Applications of Information Technology (EAIT), Nov 31 – Dec 1, 2012, pp 462 – 466.
  12. Komar, R., Bhat, M.S. and Laxminidhi, T., “Switched inverter comparator based 0.5 V low power 6 bit Flash ADC”  in proceedings of 10th IEEE International Conference on Semiconductor Electronics (ICSE), 19-21 Sept. 2012, pp 613 – 617.
  13. Rekha S. and Laxminidhi T., “Effect of parasitics of feed-forward compensated OTA on Active-RC integrators”, 3rd international conference on Advances in Power Electronics and Instrumentation Engineering (PEIE 2012), Bangalore, Aug.03-04, 2012. Vasantha M.H. and Tonse Laxminidhi, “0.5 V, 36 μW Gm -C Butterworth Low Pass Filter in 0.18μm CMOS process”, in proceedings of The Fourth IEEE Asia Symposium on Quality Electronic Design (ASQED– 2012), July 11–12, 2012, pp. 82–85.
  14. Komar R, Bhat M.S. and Laxminidhi T., “A 0.5V 300µW 50MS/s 180nm 6bit Flash ADC using inverter based comparators”, in proceedings of IEEE International Conference on Advances in Engineering, Science and Management (ICAESM), March 30-31 2012,  pp 331 – 335.
  15. VasanthaM.H. and Tonse Laxminidhi, “A 0.5V, 20 μW Pseudo-differential 500 kHz Gm-AC Low-Pass Filter in 0.18 μm CMOS Technology”, in proceedings of IEEE International Conference on Devices, Circuits and Systems (ICDCS– 2012), March 15-16, 2012, pp. 76–79.
  16. Vasantha M.H. and Tonse Laxminidhi, “20 μW, 500 kHz Continuous-Time Low- Pass Filter in 0.18 μm CMOS Process”,in proceedings of Second International Engineering Symposium -IES 2012 (KU-MIT-NITK Joint Symposium), March 5– 7, 2012, pp. E1-3-1–E1-3-6.
  17. Prajakta Panse and T. Laxminidhi ”On-Chip 1.8 V Step Down DC/DC Converter with 94% Power Efciency”, in proceedings of 3rd Asia Symposium Quality Electronic Design (ASQED) 19-20 July 2011, pp 42-45.
  18. Rekha S. and Laxminidhi T., “Low power, fully differential, feed-forward compensated bulk driven OTA”, Proc. 8th international conference organized by Electrical Engineering/ Electronics, Computer,Telecommunications and Information Technology Association(ECTI), Thailand, Thailand, May 17-19, 2011.
  19. Prajakta Panse and T. Laxminidhi ”Energy Efcient 1.8 V Step Down DC/DC Converter in 0.18 µm CMOS Technology with optimized silicon area”, 3rd International Conference on Electronics Computer Technology - ICECT 2011 proceedings, April 2011.
  20. Rekha S. and Laxminidhi T., “A low power, fully differential bulk driven OTA in 180 nm CMOS Technology”, Proc. 3rd international conference on Signal acquisition and Processing, Singapore, Feb. 26-28, 2011.
 

Contact us

Dr. T. Laxminidhi,  Professor and Head, 
Department of E&C, NITK, Surathkal
P. O. Srinivasnagar,
Mangalore - 575 025 Karnataka, India.

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