R&D Project:
On-going:
- Co-chief investigatorfor MeitY sponsored project – “Special Manpower Development Project - Chips to System Design (SMDP-C2SD)” – 2015-2020.
- Co-Investigator for IMPRINT project “Development of cost effective Radiofrequency ablation system and magnetic hyperthermia equipment for thermal therapies
- of cancerous rumors", funded by Science and Engineering Research Board (SERB) with an outlay of Rs. 45.94 Lakhs, 2019-2021.
Completed:
1. Co-investigator TEQIP-III sponsored R&D project on “Design, Development and Commissioning of Automatic Warning System for Unmanned Level Crossings of Indian Railways - in Collaboration with Southern Railways, Palakkad Division.” with an outlay of Rs. 4 Lakhs (2016-17).
- Co-investigator for DIT sponsored R&D project titled “RF MEMS Switches for Wide-band Reconfigurable RF Micro-systems”. The cost of the project is Rs. 175 Lakhs, (2010-2013).
Consultancy Activities
Technical Consultant to Corporation Bank, Syndicate Bank and Vijaya Bank for the procurment of Note Sorting Machines with Counterfeit note detection capability . – Since 2009 for purchasing Currency Sorting Machines The total consultancy revenue earned is about Rs. 60 Lakhs. The consultancy involved
(a) Framing the technical specifications
(b) Technical evaluation of the received tenders
(c) Framing Stress test procedure for carrying out stress tests on two machines of each vendor who is qualified in the Technical evaluation of the tender.
(d) Carrying out critical stress tests on the machines
(e) Bring out any shortfalls in machines to the authorities of Corporation Bank.
(f) Recommending the machines, which have qualified the stress test, for the opening of financial bids.
ASIC Chip Designs
- Designed Three ASIC chips as part of Ph.D. thesis.
(a) 2 chips : 70MHz-500 MHz programmable bandwidth Chebyshev low-pass continuous time Gm-C filters designed in 350 nm CMOS process
(b) 44 MHz – 300 MHz programmable bandwidth Chebyshev low-pass continuous time Active-RC filter designed in 180 nm CMOS process.
2. India Chip Program Program (Funded by SMDP-VLSI Project)
Designed a 2 Msps Successive Approximation Register ADC in 180 nm CMOS technology. The Chip had 3 designs, two from NITK (one analog design and one digital design) and one from NIT Tiruchirapalli. The chip designed in 180 nm CMOS process from UMC Technologies was integrated at NITK.
3. Designs of two of my Ph.D. Students and one M.Tech. (Research) student have been realized on silicon as a single chip in 180 nm process from UMC Technologies.
4. Chip as part of SMDP-C2SD : A Phase-Locked Loop was designed for generating 100 MHz clock and fabricated through Semiconductor Laboratory.
RF MEMS Switches for Wideband Reconfigurable RF Microsystems
· Role: Co-investigator (Chief Investigator : Dr. M.S. Bhat)
· Sponsoring Agency: Department of Electronics and Information Technology (DeitY), 6, CGO complex, New Delhi.
· Project Outlay: Rs. 175 Lakhs
· Project Duration: 3 years, 6 months (July 2010 to December 2013)
· Status: Completed